In the automated testing of solid state read/write memories, a thorough performance test thereof requires more than the conventional instantaneous "snap-shot" check for the proper state of such a memory's output, as typically determined at the leading edge of each of a succession of test set-generated strobe pulses. More specifically, there should be a comprehensive test to ascertain not only if each test set-initiated memory output state is initially valid, but remains valid, i.e., if "ones" remain above a minimum threshold voltage, and if "zeros" remain below a maximum threshold voltage, throughout each test set-established Data Valid Period (DVP), or so-called time window.
Such a comprehensive test is very important because in a typical operating system environment, successive points in time when a memory residing therein will be strobed for data may vary appreciably due to unpredictable inherent system delays, such as may be caused by component tolerance variations, or extraneous noise. As such, it becomes very important to ascertain if the output state of a given memory will remain relatively constant throughout a test set-determined time window that encompasses, and appreciably extends beyond either side of, the expected pulse width-defined strobe period of the composite system.
In connection with the "snap-shot" approach to checking for the proper memory output state (i.e., at the trailing edge of a test set-generated strobe pulse), it should be apparent, of course, that one could repeat such a "snap-shot" test while varying the strobe position. Unfortunately, this would not guarantee that each memory output signal (or data bit) remained within specified limits for the entire window interval. Moreover, such variable strobe-position testing would disadvantageously appreciably lengthen the test time.
Inasmuch as present automated test sets are not adapted to provide the thorough testing of a memory's output state in the manner described above, and of concern herein, an auxiliary test circuit has been urgently needed to carry out such a testing operation on an output data bit-per line basis. In this regard, it is also very important that any auxiliary test circuit be of a type that is readily controlled by an associated test set, and can test the output state of each line of a memory at the normal operating speed thereof, and provide pass/fail output result signals that are compatible with the associated test sets built-in detection circuitry. In addition, it is very desirous that such pass/fail outputs remain available for examination by the test set at any time between the end of each time window test interval and the start of the next test cycle.